ARM announces Cortex-A35, its new ultra-efficient 64-bit core

That is a total of just 3 processor designs (without the A35), however when you look at the 32-bit space, ARM offers 6 different core designs ranging from the very low power Cortex-A5 right up to the high performance Cortex-A15 and Cortex-A17 cores. In rough, general terms the 64-bit Cortex-A53 is targeted at the same market segment as the 32-bit Cortex-A9 processor, however there is still room (in terms of power efficiency) below that, a space which is filled by the Cortex-A5 and Cortex-A7 in ARM’s 32-bit lineup, however there was nothing in the 64-bit lineup. That is where the Cortex-A35 comes in.

Processors based on the Cortex-A35 will be cheaper than those which use the higher performing cores, like the Cortex-A72, and since they are designed for high levels of power efficiency, it would mean that smartphone makers can use smaller (i.e. cheaper) batteries.

In terms of its capabilities and performance, the Cortex-A35 is a 64-bit processor that is fully compatible with ARM’s other Cortex designs. It uses around 10% less power than the Cortex-A7 while offering between 6 and 40% more performance. When compared to the Cortex-A53, the die size for the Cortex-A35 is 25% smaller while using 32% less power.

It is also big.LITTLE compatible which means it could be used in conjunction with a Cortex-A72 or Cortex-A57. I wouldn’t be surprised if some SoC makers end up sticking it together with the Cortex-A53, i.e. four Cortex-A35 cores coupled with four Cortex-A53 cores. Or if MediaTek keeps developing its tri-cluster technology then we could see a SoC with four Cortex-A35 cores, four Cortex-A53 cores and two Cortex-A72 cores!

Deep dive

The Cortex-A35 uses an in-order pipeline (as does the Cortex-A7 and the Cortex-A53), however ARM has resigned the front end to include better branch prediction, better balanced instruction fetch bandwidth, and a smaller, more power efficient instruction queue. It also has a 512-entry translation lookaside buffer (TLB), up from 256 entries in the Cortex-A7. The TLB is used by the Memory Management Unit (MMU) to speed up virtual address translation.

The new design is also highly scalable. By that ARM means that its partners can design quad-core processors (with 32K of L1 cache, 1MB of L2 cache along with the NEON engine), down to a single core processor (with just 8K of L1 cache and no L2 cache). The single core variant would be just 0.4 square millimeters when built using a 28nm process node, which is 10 times smaller than the quad-core setup.

The quad-core version would use less than 90mW at 1.0GHz where as the single core version would use less than 6mW at 100MHz. Now 100Mhz is not a number you would quote when talking about smartphones, however the flexibility of the Cortex-A35 design means that OEMs can make processors that not only target smartphones (at 1GHz and upwards) but also IoT devices. These IoT devices would benefit from having a full 64-bit processor with support for hardware encryption instructions while running a low speeds and using less power. Not only that, but such a processor would be fully backwards compatible with existing software and could run operating systems line Android, Linux and Brillo.

Wrap up

So in a nutshell, the Cortex-A35 is ARM’s most efficient applications processor design. It brings 64-bit computing to the ultra-power efficient category while being scalable enough to be used in big.LITTLE octa-core processors or whittled right down to single-core 100MHz devices, with almost microcontroller type power requirements.

The design for the core is now with ARM’s partners and you can expect to see devices with SoCs that include the Cortex-A35 some time towards the end of 2016.